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Jerry Xiao One
  2025-01-04 16:03:00   2025-01-15 11:32:31  

Here I will constantly some of the projects I have been working on and the corresponding description of the projects. Currently, my interest mainly lies in the field Distributed System and Machine Learning. I am a participant for various super computing competition and I am thrilled to apply the power of supercomputer into solving some of the Machine Learning problems.

CS109 Jungle Java github

Contributors:

  1. Mengxuan Wu
  2. Yicheng Xiao

The project of CS109 aims at creating an interactive Jungle. During the project, we have realized the basic function, the AI module (Mengxuan Wu has implemented the hard AI with Monte Carlo Tree Search, Yicheng Xiao has implemented the medium AI with min-max algorithms with alpha-beta pruning). Mengxuan Wu has further realized the multiplayer modes. Yicheng Xiao is responsible for the GUI.

CS211 Electronic Organ Verilog github

Contributors:

  1. Mengxuan Wu
  2. Shengli Zhou
  3. Yicheng Xiao

It is asked to implemented a Electronic Organ using FPGA board with verilog. Mengxuan Wu accounts for the memory module. Shengli Zhou accounts for input module and the state machine of the whole game. Yicheng Xiao accounts for Buzzer and VGA modules.

In the project, the Buzzer can support from C3 to C5 and can produce multiple notes at the same time. The VGA has been realized to top up the engagement of the game.

CS214 Pipelined CPU Verilog github

Contributors:

  1. Yicheng Xiao
  2. Shengli Zhou
  3. Haibin Lai

We have designed a pipelined RISC-V CPU with the following structure:
Pipeline Structure

We have realized the following instructions:

InstructionEncodingData FlowUsage
R-Type InstructionOpcode: 0110011
addfunct7: 0x00 funct3: 0x0Register(rs1, rs2) -> ALU -> WB -> Register(rd)add rd, rs1, rs2
xorfunct7: 0x00 funct3: 0x4Register(rs1, rs2) -> ALU -> WB -> Register(rd)xor rd, rs1, rs2
andfunct7: 0x00 funct3: 0x7Register(rs1, rs2) -> ALU -> WB -> Register(rd)and rd, rs1, rs2
I-Type-Immediate InstructionOpcode: 0010011
addifunct3: 0x0Register(rs1) \ ID(Imm) -> ALU -> WB -> Register(rd)addi rd, rs1, Imm
xorifunct3: 0x4Register(rs1) \ ID(Imm) -> ALU -> WB -> Register(rd)xori rd, rs1, Imm
andifunct3: 0x7Register(rs1) \ ID(Imm) -> ALU -> WB -> Register(rd)andi rd, rs1, Imm
sllifunct3: 0x1Register(rs1) \ ID(Imm) -> ALU -> WB -> Register(rd)slli rd, rs1, Imm
srlifunct3: 0x5Register(rs1) \ ID(Imm) -> ALU -> WB -> Register(rd)srli rd, rs1, Imm
I-Type-Load InstructionOpcode: 0000011
lbfunct3: 0x0Register(rs1) \ ID(Imm) -> ALU -> DMem -> WB -> Register(rd)lb rd, Imm(rs1)
lbufunct3: 0x4Register(rs1) \ ID(Imm) -> ALU -> DMem -> WB -> Register(rd)lbu rd, Imm(rs1)
lwfunct3: 0x2Register(rs1) \ ID(Imm) -> ALU -> DMem -> WB -> Register(rd)lw rd, Imm(rs1)
I-Type-Jump InstructionOpcode: 1100111
jalrfunct3: 0x01. Register(rs1) \ ID(Imm) -> ALU -> IFjalr rd, Imm(rs1)
2. IF(PC) -> ID -> ALU -> WB -> Register(rd)
I-Type-Ecall InstructionOpcode: 1110011
S-Type InstructionOpcode:0100011
swfunct3: 0x2Register(rs1) \ ID(Imm) -> ALU -> DMem(Mem[rs1 + Imm] = rs2)sw rs2, Imm(rs1)
B-Type InstructionOpcode: 1100011
beqfunct3: 0x0Register(rs1, rs2) -> ALU -> IFbeq rs1, rs2, Label
bnefunct3: 0x1Register(rs1, rs2) -> ALU -> IFbne rs1, rs2, Label
bltfunct3: 0x4Register(rs1, rs2) -> ALU -> IFblt rs1, rs2, Label
bgefunct3: 0x5Register(rs1, rs2) -> ALU -> IFbge rs1, rs2, Label
bltufunct3: 0x6Register(rs1, rs2) -> ALU -> IFbltu rs1, rs2, Label
bgeufunct3: 0x7Register(rs1, rs2) -> ALU -> IFbgeu rs1, rs2, Label
J-Type InstructionOpcode: 1101111
jalID(Imm) -> ALU -> PC \ ID(PC) -> ALU -> WB -> Register(rd)jal rd, Label
U-Type InstructionOpcode: 0110111
luiID(Imm) -> ALU -> WB -> Register(rd)lui rd, Imm

CS305 Reliable Data Transfer Python github

Contributors:

  1. Yujun He
  2. Zhaoyang Hong
  3. Yicheng Xiao

For the socket package, we can only use the method for UDP, which is recvfrom() and sendto().
We need to use threads to maintain a “connection” between the client and the server, because the server needs to be able to handle multiple clients at once.
Each socket is binded to an address and a port, while connecting to a server, the client needs to know the address and the port of the server.
After the server gets the address and the port of the client, it will maintain a FSM with the according client to form a “connection”.

SWS3004 GroupUp React github

Contributors:

  1. Zhengdong Huang, Backend Design and Cloud Service Design
  2. Hemu Liu, Backend Design and Cloud Service Design
  3. Zihang Wu, Frontend Design
  4. Yicheng Xiao, Frontend Design and Recommender Service Design

When our class begins, we are required to find our teammates. It is not uncommon that we tend to naturally group up with someone from the same universities because of familiarity. However, by grouping up like this, we cannot even get to know each other pretty well. Then this idea comes across us: We can design a cloud-based grouping application for this scenario! We aim to design a system where you can find your teammates based on recommendation!

CS323 Incredibuild Rust github

Contributors:

  1. Ben Chen
  2. Yicheng Xiao
  3. Jiarun Zhu

SPL(SUSTech Programming Language) Compiler in Rust. Current implementation mainly focuses on Compiler frontend, including Lexer, Parser, AST, Type Checker and LLVM IR generation. The backend we use is LLVM. The grammar supported is as follows:

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// Program Structure
Program -> ProgramPart*
ProgramPart -> Stmt | FuncDec

// Declarations and Definitions
ParaDecs -> Comma<ParaDec>
StructDecs -> Comma<StructDec>
ArrayDecs -> Comma<CompExpr>
FieldsDec -> VarDef ";"?
           | FieldsDec VarDef ";"?
FuncDec -> Specifier Identifier "(" ParaDecs? ")" "{" Body "}"
DimDecs -> "[" CompExpr "]"
         | "[" CompExpr "]" DimDecs
FuncCall -> Identifier "(" ArgList? ")"
ArgList -> CompExpr | CompExpr "," ArgList
Comma<T> -> T | T "," Comma<T>

// Statements
Stmt -> "struct" Identifier "{" FieldsDec "}" ";"?
      | "include" "string"
      | Specifier VarDecs ";"
      | "if" "(" CondExpr ")" Expr
      | "if" "(" CondExpr ")" Expr "else" Expr
      | "while" "(" CondExpr ")" "{" Body "}"
      | "for" "(" VarManagement? ";" CondExpr? ";" VarManagement? ")" "{" Body "}"
      | VarManagement ";"
      | FuncCall ";"
      | "break" ";"
      | "continue" ";"
      | "return" CompExpr? ";"
      | "{" Body "}"

// Body
Body -> Expr*

// Expression
Expr -> OpenExpr | CloseExpr
OpenExpr -> "if" "(" CondExpr ")" Expr
          | "if" "(" CondExpr ")" Expr "else" OpenExpr
CloseExpr -> "if" "(" CondExpr ")" Expr "else" CloseExpr
           | WhileExpr
           | ForExpr
           | FuncCall
           | VarManagement ";"
           | "break" ";"
           | "continue" ";"
           | "return" CompExpr? ";"
           | "{" Body "}"

// While Expression
WhileExpr -> "while" "(" CondExpr ")" "{" Body "}"

// For Expression
ForExpr -> "for" "(" VarManagement? ";" CondExpr? ";" VarManagement? ")" "{" Body "}"

// Variable Management
VarManagement -> VarDef
               | VarDecs
               | Identifier DimDecs? "++"
               | Identifier DimDecs? "--"

// Variable Declarations and Definitions
VarDef -> Specifier Identifier DimDecs? "=" "{" StructDecs "}"
        | Specifier VarDecs
VarDecs -> VarDec | VarDec "," VarDecs
VarDec -> Identifier DimDecs?
        | Identifier DimDecs? "=" CompExpr
        | StructRef "=" CompExpr
        | Identifier DimDecs? "=" "{" ArrayDecs "}"
StructRef -> StructRef "." Identifier DimDecs?
           | Identifier DimDecs? "." Identifier DimDecs?

// Conditional Expression
CondExpr -> CondTerm
          | "!" CondExpr
          | CompExpr ">" CompExpr
          | CompExpr "<" CompExpr
          | CompExpr ">=" CompExpr
          | CompExpr "<=" CompExpr
          | CompExpr "==" CompExpr
          | CompExpr "!=" CompExpr
          | CondExpr "&&" CondExpr
          | CondExpr "||" CondExpr
CondTerm -> "bool"
          | "(" CondExpr ")"

// Computation Expression
CompExpr -> Term
          | CompExpr "%" CompExpr
          | CompExpr "*" CompExpr
          | CompExpr "/" CompExpr
          | CompExpr "+" CompExpr
          | CompExpr "-" CompExpr
          | CompExpr "&" CompExpr
          | CompExpr "|" CompExpr
          | CompExpr "^" CompExpr

// Term
Term -> "(" CompExpr ")"
      | Identifier DimDecs?
      | "+"? "int"
      | "-" "int"
      | "+"? "float"
      | "-" "float"
      | "char"
      | "string"
      | Identifier "(" ArgList? ")"
      | StructRef
      | "&" Identifier
      | "*" Identifier

// Type Specifiers
Specifier -> "typeint"
           | "typeint" "*"
           | "typefloat"
           | "typefloat" "*"
           | "typechar"
           | "typechar" "*"
           | "typestr"
           | "void"
           | "struct" Identifier

Based on the tools we use Logos and lalrpop, we have realized self-defined error-recovery mechanism that can detect lexical errors and syntax errors. In the analyzer module, we have conducted type checking and semantic analysis. As the last step, we use inkwell to generate LLVM IR code.

CS329 When AL and DA meets at OD Python github

The full name stands for “When Active Learning and Data Augmentation meets at Object Detection”.

Contributors:

  1. Shengli Zhou
  2. Yicheng Xiao

In this project, we studied the effect of Active Learning and Data Augmentation on Object Detection. We use infromation entropy and information gain as the criterion for Active Learning. Also, we chose different levels of Data Augmentation techniques. We used RTDETR-v2 as our pre-trained model and train it on the Kitti 3D Object Detection 2017 dataset. Through our finetuning process, we observed a correlation between the selection strategy and the according data augmentation strategy that can probably give us better understanding of the learning process and guide us what data should we choose to improve the performance. Check out the report here!

AL_DA_OD

CS334 VirtIO for crypto device on Asterinas Rust github

Contributors:

  1. Jiarun Zhu
  2. Shengli Zhou
  3. Yicheng Xiao

This is a simple implementation of a VirtIO crypto device. The device is a PCI device that can be used to encrypt and decrypt data. The device is implemented in QEMU. Check out the report here!

We have implemented the following features:

  • Symmetric Algorithm
    • Cipher (Encrypt/Decrypt)
    • Chain Algorithm
      • Hash Algorithm (Encrypt/Decrypt)
      • MAC Algorithm (Encrypt/Decrypt)
  • AKCIPHER Algorithm (Encrypt/Decrypt/Sign/Verify)
  • Writing Test Cases
  • Asynchronous Request
  • User Call

Academic Record SUSTech

Course CodeCourse NameSemesterInstructorFinal Grade
MA117Calculus I2022 FallRong Wang99
MA127Calculus II2023 SpringRong Wang99
MA113Linear Algebra2022 FallYimao Chen97
CS104Introduction to Mathematical Logic2023 SpringMingxin He100
CS109Introduction to Computer Programming2023 SpringJianqiao Yu98
CS211Digital Logic (H)2023 FallYuhui Bai97
CS213Principles of Database Systems (H)2023 FallShiqi Yu96
CS214Computer Organization (H)2024 SpringYuhui Bai97
CS215Discrete Matrhematics (H)2023 FallQi Wang86
CS216Algorithm Design and Analysis (H)2024 SpringShan Chen91
CS217Data Structures and Algorithms Analysis (H)2023 FallPietro Simone Oliveto97
CS305Computer Networks2024 SpringZhuozhao Li92
CS311Artificial Intelligence (H)2024 SpringBo Yuan83
CS323Compiler2024 FallYepang Liu95
CS329Machine Learning2024 FallQi Hao
CS334Operating System2024 FallYiqian Zhang
MA212Probability and Statistics2023 FallYiwei Zhang95
  1. CS109 Jungle Java
  2. CS211 Electronic Organ Verilog
  3. CS214 Pipelined CPU Verilog
  4. CS305 Reliable Data Transfer Python
  5. SWS3004 GroupUp React
  6. CS323 Incredibuild Rust
  7. CS329 When AL and DA meets at OD Python
  8. CS334 VirtIO for crypto device on Asterinas Rust
  9. Academic Record SUSTech
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  1. CS109 Jungle Java
  2. CS211 Electronic Organ Verilog
  3. CS214 Pipelined CPU Verilog
  4. CS305 Reliable Data Transfer Python
  5. SWS3004 GroupUp React
  6. CS323 Incredibuild Rust
  7. CS329 When AL and DA meets at OD Python
  8. CS334 VirtIO for crypto device on Asterinas Rust
  9. Academic Record SUSTech